Rishit Dwivedi.
Ames, Iowa

Rishit Dwivedi

Computer Engineering student at Iowa State University

I build software across the stack — from AI-powered document intelligence and web applications to embedded systems and digital hardware.

Email me Call View projects
rishit.dwivedi05@gmail.com +1 (515)-916 0557 LinkedIn ↗
01

About

Background, education, and community involvement.

I'm a Computer Engineering student at Iowa State University, expected to graduate in December 2027. I completed my first two years of Computer Science and Engineering coursework at Nirma University in India through a 2+2 international transfer program.

My work spans AI-powered document intelligence with OCR, LLMs, and RAG; web and Android application development; and embedded C and hardware design — from robot drivers on a TM4C123 to a single-cycle RISC-V processor in VHDL.

Education

Iowa State University, College of Engineering

B.S. Computer Engineering
Expected Dec 2027
Ames, Iowa

Nirma University

Computer Science and Engineering — 2+2 International Transfer Program
2023 – 2025
Ahmedabad, India

Completed first two years of Computer Science and Engineering coursework through a 2+2 international transfer program.

Activities

Shri Hare Krishna Vridhashram

Volunteer
Summer 2024
Katni, India
  • Elder-care and old-age shelter service.
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Experience

Industry, internship, and campus roles.

AI-Powered Document Intelligence ExternCurrent

Pfizer / Forage
Aug 2026 – Present
Remote
  • Prototyped AI-powered document intelligence for enterprise PDF workflows, combining OCR, image processing, LLMs, and RAG to extract and structure information from scanned and digital documents; tools include PyMuPDF, pdfplumber, Tesseract, PaddleOCR, LlamaIndex, Mistral, Gemini, and Gradio.
  • Evaluated extracted outputs against source documents using Python and regex-based validation; documented failure cases and accuracy limitations, and mapped pharmaceutical-documentation requirements into prototype workflows and technical findings.

Production CrewCurrent

Iowa State University Athletics
Apr 2026 – Present
Ames, Iowa
  • Prepare event spaces and production equipment, coordinate with staff during live events, assist guests, and support setup, execution, and venue restoration under tight timelines.

Web Development Intern

Relax India Group
Dec 2024 – Jan 2025
Kanpur, Uttar Pradesh
  • Built and maintained customer-facing web features using Django, Python, and MySQL; translated requirements into tested interface updates and documented implementation details for handoff.
  • Investigated application defects, coordinated fixes with teammates, and verified behavior before delivery.

Web Development Intern

Varlyq Technologies
May 2024 – Dec 2024
Bangalore, India
  • Built and maintained customer-facing web features using Django, Python, and MySQL; translated requirements into tested interface updates and documented implementation details for handoff.
  • Investigated application defects, coordinated fixes with teammates, and verified behavior before delivery.
03

Projects

Selected academic and team projects across software, embedded systems, and hardware.

01

LabFlow

Frontend Design Lead · Four-Person Android Team
Jan 2026 – May 2026
  • Led frontend design and implementation of a native Android lab-workflow application, creating the visual system, reusable screens, navigation, and integration-ready interfaces for a Spring Boot/MySQL backend.
  • Specified the student Lab List and Lab Instructions screens. The app guides students through checkpoint questions, lets TAs generate an entire lab from its manual with AI, and opens 3D equipment models. Checkpoint progress, course chat and notifications stream live over STOMP WebSockets, so TA dashboards update while students work.
  • Collaborated across two frontend and two backend developers; resolved major integration issues before the final demo. Testing across three lab types measured up to 60% lab time reduction; ranked 1st in section and 2nd overall among 40+ teams.
1st in section · 2nd overall of 40+ teams
LabFlow branding preview
AndroidSpring BootMySQLWebSockets
02

Single-Cycle RV32I Processor

Structural VHDL
Summer 2026
  • Designed a single-cycle RISC-V datapath and control path in structural VHDL supporting arithmetic, load/store, branch, and jump instructions; integrated the ALU, control unit, register file, immediate generator, memory path, and PC-selection logic.
  • Verified with self-checking QuestaSim testbenches and test programs (including recursive merge sort) that match the RARS simulator with zero mismatches; synthesized with a maximum frequency of 22.69 MHz.
VHDLRISC-VQuestaSimDigital logic
Nov 2025 – Dec 2025
  • Built embedded C drivers and control logic for a TM4C123-based mobile robot using infrared and ultrasonic scanning, IMU-based turning, bumper and cliff sensing, and object-width estimation; developed a Python TCP interface for live visualization and click-to-move control.
Embedded CTM4C123PythonTCP
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Skills

Tools and technologies grouped by area.

AI / Data

Programming

Software / Backend

Embedded / Hardware

05

Contact

I'm open to internships, co-ops, and engineering opportunities. The best way to reach me is by email.

Email
rishit.dwivedi05@gmail.com
Phone
+1 (515)-916 0557
LinkedIn
in/rishitdwivedi0605 ↗
Location
Ames, Iowa